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Emulation of DPDK Running on an NXP Processor in the QEMU System
Postolka, Matěj ; Dražil, Jan (referee) ; Kořenek, Jan (advisor)
This project deals with the emulation of the networking features of the NXP QorIQ LS2088A processor for the purpose of testing Data Plane Development Kit (DPDK) applications. These networking features are emulated as a virtual PCI device in the QEMU machine emulator. This PCI device is compatible with the DPDK and supports the features offered by the original NXP QorIQ LS2088A hardware, thus providing a virtual environment for testing DPDK applications designed for the original NXP QorIQ LS2088A hardware.
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Network Traffic Analysis Using NXP Processor and FPGA
Orsák, Michal ; Vrána, Roman (referee) ; Kořenek, Jan (advisor)
The primary goal of this thesis is to exploit possibilites of aa entirely new hardware based on NXP LS2088 and FPGA. The secondary goal is to create firmware for this processor working out-of-box and perform optimisations of existing software for L7 analysis. This software was deeply bound to a previous hardware platform. The network processor NXP LS2088 contains many hardware accellerators and a virtual reconfigurable network. This thesis exploits all hardware parts of on this platform. Many tweaks and optimizations were performed based on this analysis to achieve maximum efficieny of software for L7 analysis. There were many intensive optimisations like rewriting for the DPDK library and new hardware or hardware synchronization of worker threads of this application. The main result of this thesis is working platform with efficient L7 analysis software which actively uses accelerators in FPGA and NXP network processor. SDK for new platform is also prepared.
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Decompilation of AArch64 Binaries in RetDec Decompiler
Kašťák, Matej ; Křivka, Zbyněk (referee) ; Kolář, Dušan (advisor)
The goal of this thesis is to propose and implement a decompiler for the AArch64 architecture. The thesis firstly introduces the concept of reverse engineering, then analyzes the ARM processor platform and architecture of RetDec decompiler from Avast company. In the next chapters, we describe the design and implementation of a module for RetDec. The~purpose of this module is to decompile machine code into LLVM IR instructions which are further processed by LLVM passes. This leads to decompilation to a higher level language.
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Decompilation of AArch64 Binaries in RetDec Decompiler
Kašťák, Matej ; Křivka, Zbyněk (referee) ; Kolář, Dušan (advisor)
The goal of this thesis is to propose and implement a decompiler for the AArch64 architecture. The thesis firstly introduces the concept of reverse engineering, then analyzes the ARM processor platform and architecture of RetDec decompiler from Avast company. In the next chapters, we describe the design and implementation of a module for RetDec. The~purpose of this module is to decompile machine code into LLVM IR instructions which are further processed by LLVM passes. This leads to decompilation to a higher level language.
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Emulation of DPDK Running on an NXP Processor in the QEMU System
Postolka, Matěj ; Dražil, Jan (referee) ; Kořenek, Jan (advisor)
This project deals with the emulation of the networking features of the NXP QorIQ LS2088A processor for the purpose of testing Data Plane Development Kit (DPDK) applications. These networking features are emulated as a virtual PCI device in the QEMU machine emulator. This PCI device is compatible with the DPDK and supports the features offered by the original NXP QorIQ LS2088A hardware, thus providing a virtual environment for testing DPDK applications designed for the original NXP QorIQ LS2088A hardware.
|
|
|
Network Traffic Analysis Using NXP Processor and FPGA
Orsák, Michal ; Vrána, Roman (referee) ; Kořenek, Jan (advisor)
The primary goal of this thesis is to exploit possibilites of aa entirely new hardware based on NXP LS2088 and FPGA. The secondary goal is to create firmware for this processor working out-of-box and perform optimisations of existing software for L7 analysis. This software was deeply bound to a previous hardware platform. The network processor NXP LS2088 contains many hardware accellerators and a virtual reconfigurable network. This thesis exploits all hardware parts of on this platform. Many tweaks and optimizations were performed based on this analysis to achieve maximum efficieny of software for L7 analysis. There were many intensive optimisations like rewriting for the DPDK library and new hardware or hardware synchronization of worker threads of this application. The main result of this thesis is working platform with efficient L7 analysis software which actively uses accelerators in FPGA and NXP network processor. SDK for new platform is also prepared.
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